I. Field of the Invention
The present invention relates generally to transistors and, more particularly, to a hetero-junction tunneling FET transistor in which the tunneling effect occurs vertically through the semiconductor layers.
II. Description of Material Art
While there are many variations of field effect transistors (FET), in general the previously known field effect transistors include a layer of doped material deposited on a substrate, such as a silicon substrate, so that the conductive semiconductor material forms a source at one end and a drain at the other. A metallic gate is positioned in between the source and the drain and is often insulated from the conductive layer by an insulating layer. Modulation of the voltage applied to the gate then varies the current flow between the source and the drain as a function of the gate voltage.
These previously known field effect transistors, however, all suffer a number of common disadvantages. One disadvantage is that, since the source and drain are necessarily spaced apart from each other, the conduction of electrons between the source and the drain is likewise necessarily lengthy. As a result, transistor noise results as well as relatively slow transistor switching.
A still further disadvantage of the previously known field effect transistors is that an application of relatively large gate voltages was required in order to adequately render the layer between the drain and the source conductive. This, in turn, results not only in increased power usage and consumption, but also heat dissipation of the transistor.